A typical Serial ATA system includes a host, a device and a communications medium that connects the host to the device. The host typically includes processing circuitry, volatile high-speed memory, and a host-side controller or concentrator. The device is typically a data storage unit (e.g., a disk drive). The communications medium (e.g., Serial ATA communications cabling) connects the host-side controller to the device and carries signals between the host and the device in accordance with the Serial ATA interface specification. In some Serial ATA systems, the host-side controller (e.g., a host bus adapter, a RAID controller, etc.) is configured to communicate with more than one device.
For a host and a device to properly exchange information, the host-side controller establishes a communication link (i.e., Physical Layer (PHY) communication) with the device through the communications medium. Once the host-side controller establishes this communication link, the host and the device are capable of exchanging commands, status and data in accordance with a normal operating mode as specified by the Serial ATA interface specification.
To establish the communication link between the host and the device (i.e., for successful PHY initialization), the host and the device perform a Serial ATA startup sequence by exchanging a set of Out-of-Band (OOB) signals through the communications medium, i.e., a Serial ATA communications cable. These OOB signals include a COMRESET signal, a COMINIT signal, a COMWAKE signal, and ALIGN primitives. To this end, the host issues and releases the COMRESET signal on the Serial ATA communications cable. When the device detects issuance and release of the COMRESET signal, the device issues the COMINIT signal. Next, the host calibrates and issues the COMWAKE signal. The device then similarly calibrates and issues the COMWAKE signal. Following the exchange of COMWAKE signals, the host and the device output and lock onto each others ALIGN sequences. At this point, the communications link is established between the host and the device and normal communications may begin. Further details of this initialization sequence is available in a document entitled “Serial ATA: High Speed Serialized AT Attachment”, Revision 1.0a, Jan. 7, 2003, the teachings of which are hereby incorporated by reference in their entirety.
Some Serial ATA systems include two hosts for fault tolerance purposes, i.e., a first host which is configured to perform normal operations and a second host which is configured to become active in place of the first host if the first host should fail. Here, the first host establishes a communications link with a device using the above-described Serial ATA startup sequence, and performs data storage operations with the device. If the first host subsequently fails, the communications link between the first host and the device is destroyed. The second host then establishes a new communications link with the device using the above-described Serial ATA startup sequence, and performs data storage operations with the device thus enabling the system as a whole to continue operation. Although the amount of time which passes between transition of control from the first host to the second host may be on the order of several hundred milliseconds to a few seconds, this amount of time is typically deemed satisfactory since the benefit of continued system operation outweighs the loss of system availability during this amount of time.